Design of an electronic circuit, for example, an integrated circuit (IC), is a complicated and time consuming process. FIG. 1 illustrates a typical design flow 100 of an integrated circuit device from conception through the generation of a fabrication ready design layout. Generally, the design flow 100 starts with defining the design specifications or requirements such as required functionality and timing at step 102. The requirements of the design are implemented, for example, as a netlist or electronic circuit description at step 104. The implementation may be performed by, for example, schematic capture (drawing the design with a computer aided design tool) or more typically, utilizing a high level description language such as VHDL, Verilog®, and the like. The implemented design is simulated to verify design accuracy at step 106. Design implementation and simulation are iterative processes. For example, errors found by simulation are corrected by design implementation and re-simulated.
Once the design is verified for accuracy with simulation, a design layout of the design is created at step 108. The design layout describes the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication. The design layout is very tightly linked to overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances, and the silicon area which is used to realize a certain function. The detailed design layout requires a very intensive and time-consuming design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
The design layout is checked against a set of design rules in a design rule check (DRC) at step 110. The created design layout must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart the geometries on various layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule may be, for example, a minimum spacing amount between geometries and is typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries may be specified for different sizes of geometries. DRC is a time-consuming iterative process that often requires manual manipulation and interaction by the designer. The designer performs design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC clean (violation free) design.
Circuit extraction is performed after the design layout is completed and error free at step 112. The extracted circuit identifies individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present. A layout versus schematic check (LVS) is performed at step 114, where the extracted netlist is compared to the design implementation created in step 104. LVS ensures that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, etc. must be corrected in the design layout before proceeding to post-layout simulation at step 116. The post-layout simulation is performed using the extracted netlist which provides a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. Once post-layout simulation is complete and all errors found by DRC are corrected, the design is ready for fabrication and is sent to a fabrication facility.
As electronic circuit densities increase and technology advances, for example, in deep sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and manufacturability and reliability of the circuit. For example, the density of a layer may be increased, additional vias may be added to interconnection areas, and the like. Creation of a design layout and performing DRC become critical time consuming processes. Performing a DRC and manipulation of the design layout often requires manual interaction from the designer. More reliable and automated techniques for improving the design layout are consistently desired.
In a modern semiconductor design technology, complex, custom circuits often require very specific, aggressive layout design rules. These rules are typically very difficult to verify with automated DRC software (i.e., DRC tool). FIG. 2 shows a conventional solution to this problem. As shown, for a design layout database 202 which includes a complex circuit, complex custom rules may be written into a DRC rules file 204 for a DRC tool 206. A special masking layer may be added to a design layout to identify to the tool 206 which areas of the chip need the special rule checks. After the DRC tool 206 completes the check, an error results database 208 may be used to store the result. When the rules are too complex, manual inspection may substitute for automated DRC software. However, complex custom rules are very difficult and time consuming to write and verify. In addition, manually adding masking layers to the design layout is an error prone process. Moreover, manual inspection of the layout database is also an error prone process.
Thus, it would be desirable to provide a system and method which may effectively address the foregoing-described problems.